Fedor G. Pikus
8625 SW Sorrento Rd
Beaverton, OR 97008
E-mail: fpikus@gmail.com
WWW: http://www.pikus.net/~pikus/
Office: (503) 685-4857
Mobile: (503) 516-0671
Home: (503) 641-0306
FAX: (503) 685-1239
SUMMARY
Senior software architect with extensive experience in EDA software development, project leadership, broad background in software architecture and engineering, programming, numerical analysis, recognized C++ expert, looking for a challenging job demanding problem solving skills and creativity.
EXPERTISE SUMMARY
EDA tools, deep submicron physical IC verification, Design for Manufacturing (DFM).
Technical team leadership, project leadership, problem and crisis solving, customer negotiations.
Software design and architecture, software development process, software education.
Numerical analysis, graph algorithms, extremely large data sets, modeling, optimization, stochastic algorithms, statistical computations, parallel programming, data structures.
Expert in C++ and Linux, broad background in programming languages, operating systems, and computing hardware.
Author of 20 publications and conference presentations on EDA, C++, and software design.
Author of 19 issued or filed patents.
PROFESSIONAL EMPLOYMENT
April 2005 - present time: Chief Software Architect for Calibre LVS, DFM, and LFD, Principal Software Engineer, Mentor Graphics, Wilsonville, Oregon.
Technical leader of a team of over 25 software developers; provided technical leadership, long-term vision, training and guidance, help in professional growth.
Maintained long-term relationships with key customers, visited customers for discussions, presentations and negotiations, persuaded customers to choose our solutions over competitors'.
Built a new software development team from the ground up, including hiring, training, technical direction, and project management; the team was aimed at entering the emerging market of Design for Manufacturing and successfully launched new EDA product, Calibre DFM.
Assembled and lead cross-functional teams from different groups, including software development, marketing, testing, documentation, and customer support, to address specific customer needs.
Designed new software framework for DFM applications which became the centerpiece of the Calibre DFM product.
Invented novel approach to physical verification, equation-based design rule checking (eqDRC); this approach is now adopted by all major foundries and large integrated device manufacturers for verification of deep submicron chips.
Invented new methodology for physical verification and layout optimization, programmable DRC; this methodology is now being adopted by a leading microprocessor manufacturer for their most advanced IC fabrication process.
Lead development of next-generation algorithms for Layout-vs-Schematic (LVS) circuit comparison and the implementation of the LVS software.
Created flexible programmable architecture for modeling of various aspects and behaviors of integrated circuits, including advanced device modeling; the architecture was successfully applied to modeling of strain silicon effects by major foundries and integrated device manufacturers.
Designed new electrical rule checking (ERC) tool, programmable ERC, lead its development and drove its adoption for ERC verification and electrostatic discharge (ESD) rules verification; created new architecture for an ESD/ERC framework and tool integration.
Invented new algorithm for topological graph-based pattern matching, lead implementation of the pattern-matching tool for DRC and physical verification.
Recognized expert on C++ with several conference presentations; taught advanced C++ classes for company employees; organized training in C++ and software engineering.
January 1998 – April 2005: Staff Software Engineer, Mentor Graphics, Wilsonville, Oregon.
Invented and implemented novel approach to LVS circuit comparison, LVS logic injection.
Designed and implemented leading layout-vs-schematics verification tools.
Designed and implemented encryption and secure data handling support for Calibre physical verification tools.
Developed and implemented hierarchical algorithms for physical verification tools.
Worked as a part of the team to make our software the leading tool in the deep-submicron physical verification.
Provided rapid responses to the issues raised by support and sales (platform-specific issues, bug fixes, benchmark optimizations, etc).
Played leading role in porting of our software to Linux and several other platforms.
July 1996 - December 1997: Research scientist, State University of New York at Stony Brook.
Developed software for modeling of semiconductor devices.
September 1994 - July 1996: Research associate, University of California at Santa Barbara
Developed leading edge stochastic and simulation algorithms and wrote highly optimized implementation for different hardware platforms, including parallel computers and supercomputers.
Developed new algorithms for parallel computing.
September 1991 - September 1994: Postdoctoral research associate, University of Utah.
Designed and optimized Monte-Carlo, linear algebra, optimization, and other algorithms, and implemented them workstations, vector supercomputers, and parallel computers.
Developed automatic load balancing algorithms for distributed memory parallel computers.
Provided computational support for our group.
EDUCATION
Ph.D. in Applied Physics: A. F. Ioffe Institute; St. Petersburg, Russia, 1992 (thesis on Computational Physics).
MS in Physics and Engineering (honors): Leningrad PolyTechnical Institute, Leningrad, Russia. February 1990.